AMS verification methodology depends on the chip type. It means that the chip can either have a big analog circuit and small digital circuit or it has a big digital circuit and small analog circuit. If the design is big analog and small digital, then the analog design library should have schematic views for simulation speed up. Simulation speed-up views can be developed from analogia with Cadence Virtuoso flow. For digital-centric design, model development is done with de facto standard model development language such as system Verilog with net types. Thus, for analog-centric design co-simulation is a good choice. For digital-centric design, simulation in the digital kernel is ideal.

Conclusion

At eInfochips, we have verified sensor-based chips with Big A and Small D designs of the chips. We have also developed model and model validation of the DDR4 data buffer. We have expertise in both mixed-signal verification and model development and model validation. To know more please contact our experts today.